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                  <h2 class="breadcrumb__title">Our Instructor</h2>
                  <p class="breadcrumb__desc">Dr. Arup Polley</p>
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                        <h3 class="xb-item--name">Dr. Arup Polley</h3>
                        <ul class="xb-item--list list-unstyled mb-20">
                           <li><span>Responsibility:</span> Associate Professor</li>
                           <li><span>Email:</span> aruppolley@iisc.ac.in</li>
                           <li><span>Years in IISc:</span> 4 years</li>
                           <li><span>Total PhD Graduated:</span> 0</li>
                           <li><span>Total Journal Papers:</span> Nil</li>
                           <li><span>Total Conference Papers:</span> Nil</li>
                           <li><span>Total Patents:</span>Nil </li>
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                        <h3 class="team-single__social-title">Important Links:</h3>
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                           <li><a href="https://in.linkedin.com/in/arup-polley-18408145"><i class="fab fa-linkedin-in"></i></a></li>
                            <li><a href="https://labs.dese.iisc.ac.in/quclassiclab "><i class="fa fa-flask"></i></a></li>
                            <li><a href="https://scholar.google.com/citations?user=J6F6kg0AAAAJ&hl=en"><i class="fa fa-graduation-cap"></i></a></li>
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                  <!--   <h2>Research Thrust:</h2>-->
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                  <!--      Digital Systems, VLSI, High Performance Accelerators, Computer Networks, Embedded Systems-->
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                  <!--   <hr class="team-single__hr">-->
                  <!--   <h2  class="mt-40">Top 20% Publications:</h2>-->
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                  <!--      <ol class="ieee-ref">-->
                  <!--         <li>Shubham Yadav, Manish Kumar, Sajin S, Shubham Sunil Garg and Kuruvilla Varghese, “Synchronization Support in 64-bit Out-Of-Order Superscalar Dual-Core RISC-V Processor”, 2024 IEEE 9th International Conference for Convergence in Technology (I2CT), Pune, India, 2024, pp. 1-7.-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/10543746" target="_blank">https://ieeexplore.ieee.org/document/10543746</a>-->
                  <!--         </li>-->
                  <!--         <li>Ajay S, Praveen V S and Kuruvilla Varghese, “An FPGA based Accelerator of the Bi-directional Wavefront Algorithm for Pairwise Sequence Alignment”,19th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2023), Hyderabad, 19-22 November 2023.-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/10509910/" target="_blank">https://ieeexplore.ieee.org/document/10509910/</a>-->
                  <!--         </li>-->
                  <!--         <li>Sadhu Sai Ram and Kuruvilla Varghese, “Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder”,19th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2023), Hyderabad, 19-22 November 2023.-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/10509943" target="_blank">https://ieeexplore.ieee.org/document/10509943</a>-->
                  <!--         </li>-->
                  <!--         <li>Bhanu Prasad A and Kuruvilla Varghese, “High Throughput Hardware Acceleration for Image Generation using HLS”,19th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2023), Hyderabad, 19-22 November 2023.-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/10509914" target="_blank">https://ieeexplore.ieee.org/document/10509914</a>-->
                  <!--         </li>-->
                  <!--         <li>Madhu Ennampelli and Kuruvilla Varghese, “Resource Efficient TCAM Implementation using SRAM”, IEEE EDS Mini-Colloquium and 3rd International Conference on Micro/Nanoelectronics Devices, Circuits, and Systems (MNDCS-2023), NIT Silchar, Assam, India. 29-31 Jan 2023. (Honorable Mention Award)-->
                  <!--            <a href="https://link.springer.com/chapter/10.1007/978-981-99-4495-8_15" target="_blank">https://link.springer.com/chapter/10.1007/978-981-99-4495-8_15</a>-->
                  <!--         </li>-->
                  <!--         <li>Sajin S, Shubham Sunil Garag, Anuj Phegade, Deepshikha Gusain, and Kuruvilla Varghese “Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core”, 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), 2023, Hyderabad, India, 8-12 Jan 2023.-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/10089948" target="_blank">https://ieeexplore.ieee.org/document/10089948</a>-->
                  <!--         </li>-->
                  <!--         <li>Ramakant Joshi, Kuruvilla Varghese, “High-Level Synthesis of Geant4 Particle Transport Application for FPGA” 25th Euromicro Conference on Digital System Design (DSD), 2022, pp. 75-83, DOI: 10.1109/DSD57027.2022.00020-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/9996703" target="_blank">https://ieeexplore.ieee.org/document/9996703</a>-->
                  <!--         </li>-->
                  <!--         <li>V. Naveen Chander, Kuruvilla Varghese, “A Soft RISC-V Vector Processor for Edge-AI”, 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID), 2022, pp. 263-268, DOI: 10.1109/VLSID2022.2022.00058-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/9885953" target="_blank">https://ieeexplore.ieee.org/document/9885953</a>-->
                  <!--         </li>-->
                  <!--         <li>Dola Ram, Suraj Panwar, Kuruvilla Varghese, ” Hardware Accelerator for Capsule Network based Reinforcement Learning”, 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID), 2022, pp. 162-167, DOI: 10.1109/VLSID2022.2022.00041 (Nripendra Nath Biswas Best Student Paper Award)-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/9885863" target="_blank">https://ieeexplore.ieee.org/document/9885863</a>-->
                  <!--         </li>-->
                  <!--         <li>A. Antony, Devi. A, and K. Varghese, “High Throughput Hardware for Hoeffding Tree Algorithm with Adaptive Naive Bayes Predictor,” 2021 6th International Conference for Convergence in Technology   (I2CT),   2021,   pp.   1-6, doi:   10.1109/I2CT51068.2021.9418100.-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/9418100" target="_blank">https://ieeexplore.ieee.org/document/9418100</a>-->
                  <!--         </li>-->
                  <!--         <li>Gokulan T, Akshay Muraleedharan, and Kuruvilla Varghese, “Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA” Euromicro Conference on Digital System Design (DSD) 2020, Virtual Event, 26-28 August 2020, pp. 340-343, DOI: 10.1109/DSD51259.2020.00062-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/9217851" target="_blank">https://ieeexplore.ieee.org/document/9217851</a>-->
                  <!--         </li>-->
                  <!--         <li>A. Birari, P. Birla, K. Varghese and A. Bharadwaj, “A RISC-V ISA Compatible Processor IP,” 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, 2020, pp. 1-6, DOI: 10.1109/VDAT50263.2020.9190558-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/9190558" target="_blank">https://ieeexplore.ieee.org/document/9190558</a>-->
                  <!--         </li>-->
                  <!--         <li>Nimish Shah, Paragkumar Chaudhari, and Kuruvilla Varghese, “Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network”, IEEE Transactions on Neural Networks and Learning Systems, Volume 29, Issue 12,-->
                  <!--            pp. 5922-5934, December 2018, DOI: 10.1109/TNNLS.2018.2815085-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/8333773/" target="_blank">https://ieeexplore.ieee.org/document/8333773/</a>-->
                  <!--         </li>-->
                  <!--         <li>Sajna Remi Clere, Sachin Sethumadhavan, Kuruvilla Varghese, “FPGA Based Reconfigurable Coprocessor  for  Deep  Convolutional  Neural  Network  Training”,  2018 21st Euromicro Conference on Digital System Design (DSD), Prague, Czech Republic, August 2018, pp. 381-388, DOI: 10.1109/DSD.2018.00072-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/8491843/" target="_blank">https://ieeexplore.ieee.org/document/8491843/</a>-->
                  <!--         </li>-->
                  <!--         <li>Suseela Budi, Pradeep Gupta, Kuruvilla Varghese, Amrutur Bharadwaj, “A RISC-V ISA Compatible Processor IP for SoC”, 2018 International Symposium on Devices, Circuits and Systems (ISDCS), Indian Institute of Engineering Science and Technology, Shibpur, March 29- 31 2018, pp. 1-5, Kolkata, India. DOI: 10.1109/ISDCS.2018.8379629-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/8379629/" target="_blank">https://ieeexplore.ieee.org/document/8379629/</a>-->
                  <!--         </li>-->
                  <!--         <li>A. Dey, S. Jose, K. Varghese and S. G. Srinivasa, “A High-throughput Clock-less Architecture for Soft-Output Viterbi Detection”, 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, USA, Aug. 2017, pp. 779-782, DOI: 10.1109/MWSCAS.2017.8053039-->
                  <!--            <a href="https://ieeexplore.ieee.org/document/8053039/" target="_blank">https://ieeexplore.ieee.org/document/8053039/</a>-->
                  <!--         </li>-->
                  <!--         <li>Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Amrutur Bharadwaj, “A Custom Designed RISC-V ISA Compatible Processor for SoC”, 21st International Symposium on VLSI Design and Test (VDAT-2017), 29 June – 2 July 2017, IIT Roorkee, India, Communications in Computer and Information Science, vol 711. Springer, Singapore, pp. 570- 577, DOI: https://doi.org/10.1007/978-981-10-7470-7_55-->
                  <!--            <a href="https://link.springer.com/chapter/10.1007/978-981-10-7470-7_55" target="_blank">https://link.springer.com/chapter/10.1007/978-981-10-7470-7_55</a>-->
                  <!--         </li>-->
                  <!--         <li>Pradeep Gupta, Suseela Budi, Kuruvilla Varghese, and Amrutur Bhardwaj, “A RISC-V Compatible Processor Ip for SoC”, RISC-V International Conference, April 2017, IIT Madras, Chennai.-->
                  <!--            <a href="http://rise.cse.iitm.ac.in/ric2017/index.html" target="_blank">http://rise.cse.iitm.ac.in/ric2017/index.html</a>-->
                  <!--         </li>-->
                  <!--         <li>Siddhartha B. Rai, Srinidhi M.S., Kuruvilla Varghese, and Srividhya R “Flow Control for Onboard Solid State Recorder” 4th International Conference on Electronics and Communication Systems, 24-25 Feb 2017, Coimbatore, India, pp. 65-69-->
                  <!--            <a href="http://ieeexplore.ieee.org/document/8067838/" target="_blank">http://ieeexplore.ieee.org/document/8067838/</a>-->
                  <!--         </li>-->
                  <!--         <li>Saugata Datta, Kuruvilla Varghese, and Shayan Srinivasa, “A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA”, 29th International Conference on VLSI Design (VLSID 2016), January 4-8, Kolkata, pp. 439-444.-->
                  <!--            <a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7434993" target="_blank">http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7434993</a>-->
                  <!--         </li>-->
                  <!--         <li>Anant Devi, Maulik Gandhi, Kuruvilla Varghese, and Dipanjan Gope, “Accelerating method of moments based package-board 3D parasitic extraction using FPGA” Microwave and Optical Technology Letters, Volume 58, Issue 4, pp. 776-783, April 2016-->
                  <!--            <a href="http://onlinelibrary.wiley.com/doi/10.1002/mop.29660/abstract" target="_blank">http://onlinelibrary.wiley.com/doi/10.1002/mop.29660/abstract</a>-->
                  <!--         </li>-->
                  <!--         <li>Sriram Venkateshan, Alap Patel, and Kuruvilla Varghese, “Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 10, pp. 2221-2232, Oct. 2015-->
                  <!--            <a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6933936" target="_blank">http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6933936</a>-->
                  <!--         </li>-->
                  <!--         <li>Anant Devi, Maulik Gandhi, Kuruvilla Varghese, and Dipanjan Gope, “Hardware Accelerator for 3D Method of Moments based Parasitic Extraction”, The 2013 IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) symposium, December 2013, Nara, Japan. pp. 100- 103-->
                  <!--            <a href="http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6724399" target="_blank">http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6724399</a>-->
                  <!--         </li>-->
                  <!--         <li>Karthikeyan P, Srijith Haridas, and Kuruvilla Varghese, “Transparent FPGA based Device for SQL DDoS Mitigation” International Conference on Field-Programmable Technology 2013 (ICFTP 2013), December 2013, Kyoto, Japan. pp. 82-89-->
                  <!--            <a href="http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6718334" target="_blank">http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6718334</a>-->
                  <!--         </li>-->
                  <!--         <li>Jimit Shah, K.S. Raghunandan, and Kuruvilla Varghese, “HD Resolution Intra Prediction Architecture for H.264 Decoder” 25th IEEE International Conference on VLSI Design VLSID 2012, January 2012, Hyderabad, India. pp.107 – 112-->
                  <!--            <a href="http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6167737" target="_blank">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6167737</a>-->
                  <!--         </li>-->
                  <!--         <li>Tejasvi Anand, Yagnesh Waghela, and Kuruvilla Varghese “A Scalable Network Port Scan Detection System on FPGA” IEEE International Conference on Field-Programmable Technology (FPT’11). December 2011, New Delhi, India. pp. 1-6-->
                  <!--            <a href="http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6132712" target="_blank">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6132712</a>-->
                  <!--         </li>-->
                  <!--         <li>Gandhi Arpit, Raghavendra Adiga and Kuruvilla Varghese, “Space Efficient Diagonal Linear Space Sequence Alignment” 10th IEEE International Conference on Bioinformatics and Bioengineering (BIBE 2010) 3 June 2010, Philadelphia, pp. 244-249-->
                  <!--            <a href="http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5521681" target="_blank">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5521681</a>-->
                  <!--         </li>-->
                  <!--         <li>Vrishali Vijay Nimbalkar, and Kuruvilla Varghese, ” In-Channel Flow Control Scheme for Network-on-Chip” 16th Euromicro Conference on Digital Systems Design (DSD 2010), September 2010, France, pp. 459-466-->
                  <!--            <a href="http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5615566" target="_blank">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5615566</a>-->
                  <!--         </li>-->
                  <!--         <li>Jimit Shah, Komanduri S. Raghunandan and Kuruvilla Varghese “Area Optimized H.264 Intra Prediction Architecture for 1080p HD Resolution”, 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2010), July 2010, France, pp: 120-125-->
                  <!--            <a href="http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5540989&tag=1" target="_blank">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5540989&tag=1</a>-->
                  <!--         </li>-->
                  <!--         <li>Vikas.G, Joy Kuri, and Kuruvilla Varghese, “Power Optimal Network-on-Chip Interconnect Design”, 22nd IEEE International SOC Conference, September, 2009, Northern Ireland, UK, pp. 147-150-->
                  <!--            <a href="http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5398071" target="_blank">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5398071</a>-->
                  <!--         </li>-->
                  <!--         <li>Divyasree J, Rajashekar H, and Kuruvilla Varghese, “Dynamically Reconfigurable Regular Expression Matching Architecture” 20th IEEE International Conference on Application-specific Systems, Architectures and Processors 2008 (ASAP 2008), July 2008, Leuven, Belgium, pp. 120-125-->
                  <!--            <a href="http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4580165" target="_blank">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4580165</a>-->
                  <!--         </li>-->
                  <!--         <li>Gajanan Jedhe, Arun Ramamoorthy and Kuruvilla Varghese, “A Scalable High Throughput Firewall in FPGA”, The 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2008 (FCCM’08), April 2008, California, USA, pp. 43-52-->
                  <!--            <a href="http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4724888" target="_blank">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4724888</a>-->
                  <!--         </li>-->
                  <!--      </ol>-->
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