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                     <h2 class="breadcrumb__title">Our Instructor</h2>
                     <p class="breadcrumb__desc">Dr. Viveka Konandur Rajanna</p>
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                           <h3 class="xb-item--name">Dr. Viveka Konandur Rajanna</h3>
                           <ul class="xb-item--list list-unstyled mb-20">
                              <li><span>Responsibility:</span> Assistant Professor</li>
                              <li><span>Email:</span>krviveka@iisc.ac.in</li>
                              <li><span>Years in IISc:</span> 3.5 years</li>
                              <li><span>Total PhD Graduated:</span> 0</li>
                              <li><span>Total Journal Papers:</span> 3</li>
                              <li><span>Total Conference Papers:</span> 17</li>
                              <li><span>Total Patents:</span> 10</li>
                           </ul>
                           <h3 class="team-single__social-title">Important Links:</h3>
                           <ul class="xb-social ul_li mt-25">
                              <li><a href="https://www.linkedin.com/in/vivekakonandur/"><i class="fab fa-linkedin"></i></a></li>
                              <li><a href="https://labs.dese.iisc.ac.in/viveka/people/"><i class="fa fa-flask"></i></a></li>
                              <li><a href="https://scholar.google.com/citations?user=-y8K3b0AAAAJ&hl=en"><i class="fa fa-graduation-cap"></i></a></li>
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                     <hr class="team-single__hr">
                     <h2 class="mt-40 mb-20">Research Thrust:</h2>
                     <div class="team-single__list">
                        <p>We, at the Efficient Computing and Integrated Systems (ECIS) Lab, aim to build innovative solutions for the next generation of efficient integrated systems towards a greener and more sustainable future. This ranges from building across a wide range of abstractions from circuit design, RTL design, chip implementation, and embedded systems along with the necessary software framework. Exploratory work using FPGAs is used for feasibility studies offering quick turn-around times for system modelling and testing. Extensive analysis and simulations are used to verify designs with promising ideas being implemented in competitive technologies for silicon demonstrations and validation. Leveraging the experience of designing, fabricating, and testing systems in a wide range of technologies, we envision driving a future where we maximize positive human impact through technology while living in synergy with nature.</p>
                        <p>Our research encompasses areas of Digital and Mixed-signal VLSI design, Energy Efficient Computation for Machine-Learning Applications, Hardware for AI, Memory Design, In-Memory Computing, Human-Machine Interface, Secure Computing, and Neural-Network Accelerators.</p>
                     </div>
                     <hr class="team-single__hr">
                     <h2 class="mt-40">Top 20% Publications:</h2>
                     <div class="team-single__list">
                        <ol>
                           <li>S. Taneja, V. K. Rajanna and M. Alioto, "In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security," IEEE Journal of Solid-State Circuits, vol. 57, no. 1, pp. 153-166, Jan. 2022, doi: 10.1109/JSSC.2021.3125255.</li>
                           <li>S. Taneja, V. K. Rajanna and M. Alioto, "36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security," 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021, pp. 498-500, doi: 10.1109/ISSCC42613.2021.9366019.</li>
                           <li>V. K. Rajanna, S. Taneja and M. Alioto, "SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm," ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), Grenoble, France, 2021, pp. 127-130, doi: 10.1109/ESSCIRC53450.2021.9567830.</li>
                           <li>K. A. Ahmed, R. Yang, P. Salamani, V. Rajanna and M. Alioto, "Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems," ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference (ESSCIRC), Lisbon, Portugal, 2023, pp. 49-52, doi: 10.1109/ESSCIRC59616.2023.10268708.</li>
                           <li>J. Basu, S. Taneja, V. K. Rajanna, T. Wang and M. Alioto, "ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm," 2023 IEEE Symposium on VLSI Technology and Circuits, Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185261.</li>
                           <li>V. K. Rajanna and B. Amrutur, "A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1663-1674, May 2016, doi: 10.1109/TVLSI.2015.2469596.</li>
                           <li>V. K. Rajanna, H. Singh Raghav, T. Wang and M. Alioto, "Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks," 2022 IEEE Symposium on VLSI Technology and Circuits, Honolulu, HI, USA, 2022, pp. 144-145, doi: 10.1109/VLSITechnologyandCir46769.2022.9830158.</li>
                        </ol>
                     </div>
                     <hr class="team-single__hr">
                     <h2 class="mt-40 mb-20">Media Coverage:</h2>
                     <div class="team-single__list">
                        <h4>Network on Chip with quintupled energy efficiency for artificial intelligence applications</h4>
                        <ul>
                           <li>
                              National University of Singapore (NUS) press release
                              <ul>
                                 <li><a href="http://news.nus.edu.sg/research/five-times-more-efficient-data-transfer" target="_blank">
                                    http://news.nus.edu.sg/research/five-times-more-efficient-data-transfer
                                    </a>
                                 </li>
                                 <li><a href="https://www.facebook.com/nus.singapore/posts/10158321001208540" target="_blank">
                                    https://www.facebook.com/nus.singapore/posts/10158321001208540
                                    </a>
                                 </li>
                                 <li><a href="https://twitter.com/NUSingapore/status/1271983288584826882?s=20" target="_blank">
                                    https://twitter.com/NUSingapore/status/1271983288584826882?s=20
                                    </a>
                                 </li>
                                 <li><a href="https://twitter.com/NUSResearch/status/1271983853020872710?s=20" target="_blank">
                                    https://twitter.com/NUSResearch/status/1271983853020872710?s=20
                                    </a>
                                 </li>
                                 <li><a href="https://www.linkedin.com/feed/update/urn:li:activity:6677863428222259200/" target="_blank">
                                    https://www.linkedin.com/feed/update/urn:li:activity:6677863428222259200/
                                    </a>
                                 </li>
                              </ul>
                           </li>
                           <li>Mirage News: 
                              <a href="https://www.miragenews.com/nus-engineers-quintuple-efficiency-of-moving-data-bits-in-silicon-chips-for-artificial-intelligence-applications/" target="_blank">
                              https://www.miragenews.com/nus-engineers-quintuple-efficiency-of-moving-data-bits-in-silicon-chips-for-artificial-intelligence-applications/
                              </a>
                           </li>
                           <li>HPCWire: 
                              <a href="https://www.hpcwire.com/off-the-wire/nus-engineers-quintuple-the-efficiency-of-moving-data-bits-in-silicon-chips-for-ai-applications/" target="_blank">
                              https://www.hpcwire.com/off-the-wire/nus-engineers-quintuple-the-efficiency-of-moving-data-bits-in-silicon-chips-for-ai-applications/
                              </a>
                           </li>
                           <li>The National Tribune: 
                              <a href="https://www.nationaltribune.com.au/nus-engineers-quintuple-efficiency-of-moving-data-bits-in-silicon-chips-for-artificial-intelligence-applications/" target="_blank">
                              https://www.nationaltribune.com.au/nus-engineers-quintuple-efficiency-of-moving-data-bits-in-silicon-chips-for-artificial-intelligence-applications/
                              </a>
                           </li>
                           <li>Tech Xplore: 
                              <a href="https://techxplore.com/news/2020-06-quintuple-efficiency-bits-silicon-chips.html" target="_blank">
                              https://techxplore.com/news/2020-06-quintuple-efficiency-bits-silicon-chips.html
                              </a>
                           </li>
                           <li>EurekAlert: 
                              <a href="https://www.eurekalert.org/pub_releases/2020-06/nuos-neq061020.php" target="_blank">
                              https://www.eurekalert.org/pub_releases/2020-06/nuos-neq061020.php
                              </a>
                           </li>
                        </ul>
                     </div>
                     <hr class="team-single__hr">
                     <h2 class="mt-40 mb-20">Patents and Stats:</h2>
                     <div class="team-single__list">
                        <h4>Patents</h4>
                        <ul>
                           <li>[US’25] Y. Z. Wong, Viveka Konandur Rajanna, P. S. Salamani, H. Okuhara, and M. Alioto,
                              “Reconfigurable Processor And A Method of Improving An Efficiency Of The Reconfigurable Processor”,
                              U.S. Patent 2024-138-02, Apr 29, 2025.
                           </li>
                           <li>[EP’25] H. S. Raghav, Viveka Konandur Rajanna, T. Wang, and M. Alioto,
                              “Impedance Monitoring System”, EP4537242, European Patent Office, Apr 16, 2025.
                           </li>
                           <li>[CN’25] H. S. Raghav, Viveka Konandur Rajanna, T. Wang, and M. Alioto,
                              “Impedance Monitoring System”, CN Patent 202380052761.9, Feb 25, 2025.
                           </li>
                           <li>[CN’25] H. S. Raghav, Viveka Konandur Rajanna, T. Wang, and M. Alioto,
                              “Impedance Monitoring System”, CN Patent 202380052761.9, Feb 25, 2025.
                           </li>
                           <li>[WIPO’24] J. Basu, S. Taneja, Viveka Konandur Rajanna, T. Wang, and M. Alioto,
                              “Methods And Systems For Generating Physical Unclonable Functions”,
                              Patent No. WO 2024/253590, Dec 12, 2024.
                           </li>
                           <li>[WIPO’24] A. Gupta, S. Kumar, Viveka Konandur Rajanna, S. Taneja, and M. Alioto,
                              “System and Method for Novelty Detection in Visual Data”,
                              Patent No. WO 2024/253586, Dec 12, 2024.
                           </li>
                           <li>[US’24] S. Taneja, Viveka Konandur Rajanna and M. Alioto,
                              “Method and Apparatus for Unified Dynamic and/or Multibit Static Entropy Generation inside Embedded Memory”,
                              U.S. Patent 20240078087, Mar 7, 2024.
                           </li>
                           <li>[WIPO’23] H. S. Raghav, Viveka Konandur Rajanna, T. Wang, and M. Alioto,
                              “Impedance Monitoring System”, Patent No. WO 2023/239308, Dec 14, 2023.
                           </li>
                           <li>[EP’23] S. Taneja, Viveka Konandur Rajanna and M. Alioto,
                              “Method and Apparatus for Unified Dynamic and/or Multibit Static Entropy Generation inside Embedded Memory”,
                              EP21921521, European Patent Office, Nov 29, 2023.
                           </li>
                           <li>[SG’21] S. Taneja, Viveka Konandur Rajanna and M. Alioto,
                              “Method and Apparatus for Unified Dynamic and Multibit Static Entropy Generation inside Embedded Memory”,
                              Singapore patent application, 10202100753U, Jan 2021.
                           </li>
                        </ul>
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