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                  <h2 class="breadcrumb__title">Our Instructor</h2>
                  <p class="breadcrumb__desc">Dr. Utsav Banerjee </p>
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                        <h3 class="xb-item--name">Dr. Utsav Banerjee </h3>
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                           <li><span>Responsibility:</span> Assistant Professor</li>
                           <li><span>Email:</span> utsav@iisc.ac.in</li>
                           <li><span>Years in IISc:</span> </li>
                           <li><span>Total PhDs Graduated:</span> </li>
                           <li><span>Total Journal Papers:</span> </li>
                           <li><span>Total Conference Papers:</span> </li>
                           <li><span>Total Patents:</span> </li>
                        </ul>
                        <h3 class="team-single__social-title">Important Links:</h3>
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                            <li><a href="https://www.linkedin.com/posts/utsav-banerjee-91086b30_iisc-research-circuits-activity-7107421427863101441-GYXm"><i class="fab fa-linkedin-in"></i></a></li>
                            <li><a href="https://labs.dese.iisc.ac.in/sinesyslab/research-overview/ "><i class="fa fa-flask"></i></a></li>
                            <li><a href="https://scholar.google.com/citations?user=HVnogZIAAAAJ&hl=en&oi=ao"><i class="fa fa-graduation-cap"></i></a></li>
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                     <h2>Research breakthroughs (≤3 years)</h2>
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                         <ul>
                            <li>Unified hardware accelerator for FFT and NTT for efficient quantum-safe lattice-based cryptography in secure digital signal processing applications</li>
                        
                            <li>Low-power hardware accelerator for SQIsign isogeny-based post-quantum digital signature verification for resource-constrained IoT applications</li>
                        
                            <li>Efficient RISC-V-based hardware-software co-design of FALCON and HAWK lattice-based post-quantum digital signature schemes for embedded systems</li>
                        
                            <li>High-performance configurable hardware acceleration of quantum-inspired probabilistic computing for solving large-scale combinatorial optimization problems</li>
                        
                            <li>Efficient algorithm for plaintext-ciphertext matrix multiplication with additively homomorphic encryption and its system-level demonstration</li>
                        
                            <li>Low-power configurable side-channel-resilient hardware accelerators for elliptic curve cryptography with safe Montgomery curves</li>
                        
                            <li>High-throughput hardware acceleration of wide-block tweakable block ciphers for memory encryption in data-intensive applications</li>
                        </ul>
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                     <h2 class="mt-40">Latest News + Announcements</h2>
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                        <ul>
                            <li><strong>Research News</strong>
                                <ul>
                                    <li>Research on efficient hardware acceleration of quantum-safe isogeny-based digital signature verification and its ASIC demonstration showcased at the 2026 IEEE International Solid-State Circuits Conference (ISSCC), the most premier global forum for presenting advancements in solid-state circuits and system-on-chip designs.</li>
                        
                                    <li>Research on RISC-V-based hardware-software co-design of FALCON and HAWK lattice-based post-quantum digital signature schemes presented at the 2025 IEEE International Conference on High Performance Computing, Data and Analytics (HiPC) Workshop and the 2026 International Conference on VLSI Design (VLSID).</li>
                        
                                    <li>Research on high-performance configurable hardware acceleration of quantum-inspired probabilistic computing presented at the 2025 IEEE International Conference on High Performance Computing, Data and Analytics (HiPC) Workshop and the 2026 International Conference on VLSI Design (VLSID).</li>
                        
                                    <li>Research on low-power configurable side-channel-resilient hardware accelerators for elliptic curve cryptography presented at the 2025 IEEE International Conference on Intelligent Computing and Systems at the Edge (ICEdge).</li>
                        
                                    <li>Research on high-throughput hardware acceleration of wide-block tweakable block ciphers for memory encryption presented at the 2025 IEEE International Conference on Intelligent Computing and Systems at the Edge (ICEdge).</li>
                        
                                    <li>Research on the design and implementation of unified hardware accelerator for FFT and NTT for efficient quantum-safe lattice-based cryptography in secure digital signal processing applications presented at the 2025 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).</li>
                        
                                    <li>Research on the construction of fast plaintext-ciphertext matrix multiplication from additively homomorphic encryption and its embedded software implementation published in the IACR Communications in Cryptology.</li>
                                </ul>
                            </li>
                        
                            <li><strong>Collaborations</strong>
                                <ul>
                                    <li><strong>Academia:</strong> MIT, Boston University, UT Dallas</li>
                                    <li><strong>Industry:</strong> ABB, Texas Instruments, Intel</li>
                                </ul>
                            </li>
                        </ul>
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                     <hr class="team-single__hr">
                     <h2 class="mt-40">Achievements</h2>
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                        <ul>
                            <li><strong>Faculty awards:</strong>
                                <ul>
                                    <li>Prof. Utsav awarded the 2023 Intel Rising Star Faculty Award</li>
                                    <li>Prof. Utsav awarded the 2022 ABB Research Award in Honor of Hubertus von Grünberg</li>
                                    <li>Prof. Utsav received the Pratiksha Trust Young Investigator Award</li>
                                </ul>
                            </li>
                        
                            <li><strong>Student awards:</strong>
                                <ul>
                                    <li>Kiran received the best poster award in the Student Research Symposium at the 2025 IEEE International Conference on High Performance Computing, Data and Analytics (HiPC).</li>
                                    <li>Nigil received the best paper award at the 2025 IEEE International Conference on Intelligent Computing and Systems at the Edge (ICEdge).</li>
                                    <li>Elizabeth awarded the ESE Design Medal.</li>
                                    <li>Tarun awarded the Prime Minister’s Research Fellowship (PMRF).</li>
                                </ul>
                            </li>
                        </ul>
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                     <h2 class="mt-40">Research Labs</h2>
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                           <li class="mb-4">
                               SINESys Lab: <a href="https://labs.dese.iisc.ac.in/sinesyslab">https://labs.dese.iisc.ac.in/sinesyslab</a>  
                           </li>
                        </ul>
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                     <h2 class="mt-40">Research Highlights</h2>
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                        <ul>
                            <li>Computation on Encrypted Data</li>
                            <li>Quantum-Safe Cryptography</li>
                            <li>Efficient Encryption and Authentication</li>
                            <li>Secure Machine Learning</li>
                            <li>Emerging Compute Paradigms</li>
                        </ul>
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